EdgeCortix to Deliver Enhanced Feature-Rich Compiler for the Renesas DRP-AI AI-Accelerator with Renesas

EdgeCortix has announced the collaboration with Renesas Electronics Corporation (Renesas).

EdgeCortix has taken its industry-leading heterogeneous platform-based compiler framework MERA and created a new compiler, DRP-AI* TVM, for Renesas’ DRP-AI1 accelerator through this collaboration. The new compiler comes with associated software and tools and works in combination with Renesas’ DRP-AI tools.

EdgeCortix Delivered Key Business Outcomes via MERA collaboration with Renesas DRP-AI Tool:

Expanded Model Support: More robust AI model support (20+ models explored) with significantly enhanced flexibility and end-user ease-of-use enhancement.
ML Framework expansion: Future proofing the DRP-AI product utility, by adding PyTorch support and making the ONNX support more robust. TensorFlow support to be added in ongoing future work.
Support for Floating-point 16 bit to MERA and extended OSS tool Apache TVM. Lower-precision support being added in ongoing future work.
Performance Enhancements: Improved performance especially for models with operators shared between host CPU and DRP-AI (a new feature added with this integration work).

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